The present invention relates to a method of manufacturing a semiconductor device having MIS (Metal Insulator Semiconductor) field effect transistors (MIS-FETs), and more particularly to a method of manufacturing a semiconductor device including MIS-FETs having gate insulating films with two or more different substrate.
As semiconductor devices having MIS field effect transistors (MIS-FETs) or MOS-FETs which are typical examples thereof, a memory device such as a dynamic RAM or static RAM and an operation device using a CMOS logic circuit are provided.
At present, miniaturization of elements due to enhancement of the integration density and enhancement of the performance cannot be avoided. In order to maintain the reliability of the elements and prevent an increase in the power consumption due to an increase in the number of the elements, it becomes inevitable to lower the power supply voltage of an internal circuit in which the elements are formed.
On the other hand, in a circuit portion having an interface with the exterior, that is, in a peripheral circuit, it is necessary to take over the specification of the power supply voltage of a circuit in the exterior conventionally used even if the generations are changed and it cannot be easily changed. That is, the peripheral circuit of the interface portion in the semiconductor device is required to be operated on a voltage higher than the power supply voltage for operating the above internal circuit. Therefore, it is required to use a plurality of power supply voltages in one semiconductor device.
In order to maintain the reliability of the operation of the elements for the plurality of power supply voltages, MIS-FETs are required to be formed such that the thickness of the gate insulating film thereof will be made relatively thin for the element which is operated on a low voltage and relatively thick for the element which is operated on a high voltage. For example, in order to simultaneously attain the 3.3 V operation and 2.5 V operation, silicon oxide films with film thicknesses of approx. 9 nm and 6 nm are required.
In order to attain this, conventionally, a silicon nitride film is used as a protection film against oxidation and a portion in which a thin silicon oxide film is formed and a portion in which a thick silicon oxide film is formed are separately oxidized.
FIGS. 1 to 3 are cross sectional views for illustrating one example of a conventional manufacturing method wherein silicon oxide films with two different film thicknesses as described above are formed.
As shown in FIG. 1, an element isolation region 102 is formed on a semiconductor substrate 100 to define an element region and then the channel ion-implantation is effected after a buffer oxide film 104 is formed on the semiconductor substrate 100. In the channel ion-implantation, since the power supply voltages used for the internal circuit and the peripheral circuit are different, it is necessary to separately form openings in a portion in which a thin silicon oxide film is formed and a portion in which a thick silicon oxide film and then effect the ion-implantation in order to suppress the short channel effect and adjust the threshold voltages.
In this case, it is assumed that the left element region defined by the element isolation region 102 is used for forming elements having a thin silicon oxide film and the right element region is used for forming elements having a thick silicon oxide film.
After a silicon nitride film is formed on the buffer oxide film 104, the silicon nitride film in a region where the thick silicon oxide film (on the right side) is to be formed is removed and a silicon nitride film pattern 106 is formed only in a region where the thin silicon oxide film (on the left side) is to be formed as shown in FIG. 2A. After this, the buffer oxide film 104 is removed only in a region where the thick silicon oxide film (on the right side) is to be formed and first oxidation is effected by use of the thermal oxidation method to form a silicon oxide film (thermal oxidation film) 108 in the region where the thick silicon oxide film (on the right side) is to be formed. In the step of forming the silicon oxide film 108, a silicon oxide film with a thickness obtained by adding a difference in the film thickness between the thin silicon oxide film and the thick silicon oxide film to a film thickness removed by etching of the buffer oxide film 104 in the region where the thin silicon oxide film (on the left side) is to be formed is formed.
Next, as shown in FIG. 2B, the silicon nitride film 106 in the region where the thin silicon oxide film (on the left side) is to be formed is removed by use of a phosphorus acid solution or the like and then the buffer oxide film 104 is etched. After this, second oxidation is effected by the thermal oxidation method to form silicon oxide films (gate oxide films) 110, 112 of two different film thicknesses, that is, silicon oxide films having a desired difference in the film thickness in the right and left regions. After this, as shown in FIG. 3, gate electrodes 114 are formed and then the process is effected according to the normal MOS-FET manufacturing process.
However, in the conventional manufacturing method described above, it is necessary to effect the cleaning step for the wafer in each of the two oxidation steps and enhance the heat treatment in view of the margin of etching of the buffer oxide film. Thus, there is a problem that the process becomes complicated and the number of heat treatments and time for the heat treatment are increased.